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DS2250(T) Soft Microcontroller Module
www.dalsemi.com
FEATURES
8-bit 8051-compatible microcontroller adapts to task-at-hand: - 8, 32, or 64 kbytes of nonvolatile RAM for program and/or data memory storage - Initial downloading of software in end system via on-chip serial port - Capable of modifying its own program and/or data memory in end use High-reliability operation: - Maintains all nonvolatile resources for 10 years in the absence of VCC - Power-fail reset - Early warning power-fail interrupt - Watchdog timer Software Security Feature: - Executes encrypted software to prevent unauthorized disclosure On-chip, full-duplex serial I/O ports Two on-chip timer/event counters 32 parallel I/O lines Compatible with industry standard 8051 instruction set Permanently powered real time clock
PIN ASSIGNMENT
1
20
21
40
40-Pin SIMM
DESCRIPTION
The DS2250(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that offers "softness" in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system VCC. The internal program/data memory space is implemented using 8, 32, or 64 kbytes of nonvolatile CMOS SRAM. Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real time clock gives permanently powered timekeeping. The clock keeps time to a hundredth of a second using an on-board crystal. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power.
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112099
DS2250(T)
ORDERING INFORMATION
PART NUMBER DS2250-8-16 DS2250-32-16 DS2250-64-16 DS2250T-8-16 DS2250T-32-16 DS2250T-64-16 RAM SIZE 8 kbytes 32 kbytes 64 kbytes 8 kbytes 32 kbytes 64 kbytes MAX CRYSTAL SPEED 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz 16 MHz TIMEKEEPING? No No No Yes Yes Yes
Operating information is contained in the User's Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications.
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DS2250(T)
DS2250(T) BLOCK DIAGRAM Figure 1
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DS2250(T)
PIN DESCRIPTION
PIN 1, 3, 5, 7, 9, 11, 13, 15 17 DESCRIPTION P1.0 - P1.7. General purpose I/O Port 1
RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is not recommended. P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the 19 on board UART. This pin should not be connected directly to a PC COM port. 21 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should not be connected directly to a PC COM port. 23 P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. 25 P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. 27 P3.4 T0. General purpose I/O port pin 3.4. Also serves as the Timer 0 input. 29 P3.5 T1. General purpose I/O port pin 3.5. Also serves as the Timer 1 input. 31 P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 33 P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 35, 37 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 39 GND - Logic ground. 26, 28, 30, 32, P2.7-P2.0. General purpose I/O Port 2. Also serves as the MSB of the Expanded 34, 36, 38, 40 Address bus. 24 PSEN - Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the Bootstrap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS2250(T) is already in a reset state. The device that pulls down should be open-drain since it must not interfere with PSEN under normal operation. ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded 22 Address/Data bus on Port 0. This pin is normally connected to the clock input on a '373 type transparent latch. When using a parallel programmer, this pin also assumes the PROG function for programming pulses. 20 EA - External Access. This pin forces the DS2250(T) to behave like an 8031. No internal memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled down internally, it should be connected to +5V to use NV RAM. In a parallel programmer, this pin also serves as VPP for super voltage pulses. 4, 6, 8, 10, 12, P0.0-P0.7. General purpose I/O Port 0. This port is open-drain and can not drive a 14, 16, 18 logic 1. It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pullups. 2 VCC + - 5 volts.
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DS2250(T)
INSTRUCTION SET
The DS2250(T) executes an instruction set which is object code-compatible with the industry standard 8051 microcontroller. As a result, software development packages which have been written for the 8051 are compatible with the DS2250(T), including cross-assemblers, high-level language compilers, and debugging tools. Note that the DS2250(T) is functionally identical to the DS5000(T) except for package and the 64k memory option. A complete description for the DS2250(T) instruction set is available in the User's Guide section of the Secure Microcontroller Data Book.
MEMORY ORGANIZATION
Figure 2 illustrates the address spaces which are accessed by the DS2250(T). As illustrated in the figure, separate address spaces exist for program and data memory. Since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be accessed by the DS2250(T) CPU. The 8- or 32-kbyte RAM area inside of the DS2250(T) can be used to contain both program and data memory. A second 32k RAM is available for data only. The Real Time Clock (RTC) in the DS2250(T) is reached in the memory map by setting a SFR bit. The MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2=1, all MOVXs will be routed to this alternate memory map. The real time clock is a serial device that resides in this area. A full description of the RTC access and example software is given in the User's Guide section of the Secure Microcontroller Data Book.
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DS2250(T)
DS2250(T) MEMORY MAP Figure 2
DATA MEMORY (MOVX)
PROGRAM LOADING
The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization may be performed in one of two ways: 1. Serial Program Loading which is capable of performing Bootstrap Loading of the DS2250(T). This feature allows the loading of the application program to be delayed until the DS2250(T) is installed in the end system. 2. Parallel Program Load cycles which perform the initial loading from parallel address/data information presented on the I/O port pins. This mode is timing set-compatible with the 87C51H microcontroller programming mode. The DS2250(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS2250(T) will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at 9600, 2400, 1200, or 300 bps over the serial port. The hardware configurations used to select these modes of operation are illustrated in Figure 3.
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DS2250(T)
PROGRAM LOADING CONFIGURATIONS Figure 3
SERIAL BOOTSTRAP LOADER
The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of initially loading application software into the DS2250(T) nonvolatile RAM. Communication can be performed over a standard asynchronous serial communications port. A typical application would use a simple RS232C serial interface to program the DS2250(T) as a final production procedure. The hardware configuration which is required for the Serial Program Load Mode is illustrated in Figure 3. Port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the device in a parallel load cycle. Although an 11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, transmit, and ground wires are all that are necessary to establish communication with the DS2250(T). The Serial Bootstrap Loader implements an easy-to-use command line interface which allows an application program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the typical format which existing 8051 cross-assemblers output. The serial loader responds to single character commands which are summarized below:
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DS2250(T)
COMMAND C D F K L R T U V W Z P G
FUNCTION Return CRC-16 checksum of embedded RAM Dump Intel hex File Fill embedded RAM block with constant Load 40-bit encryption key Load Intel hex file Read MCON register Trace (Echo) incoming Intel hex data Clear Security Lock Verify Embedded RAM with incoming Intel hex Write MCON register Set security lock Put a value to a port Get a value from a port
Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated with these cycles is illustrated in the electrical specs.
PARALLEL PROGRAM LOAD CYCLES Table 1
MODE Program Security Set Verify Prog Expanded Verify Expanded Prog MCON or Key registers Verify MCON registers RST 1 1 1 1 1 1 1
PSEN PROG
EA
P2.7 1 1 0 0 0 0 0
P2.6 0 1 0 1 1 1 1
P2.5 X X X 0 0 1 1
0 0 X 0 0 0 0
0 0 X 0 1 0 1
VPP VPP 1 VPP 1 VPP 1
The Parallel Program cycle is used to load a byte of data into a register or memory location within the DS2250(T). The Verify cycle is used to read this byte back for comparison with the originally loaded value to verify proper loading. The Security Set cycle may be used to enable and the software security feature. One may also enter bytes for the MCON register or for the five encryption registers using the Program MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be verified using the Verify MCON cycle. When the DS2250(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in the Program Load Mode following a power-on reset, the internal hardware of the device is initialized so that an existing 4-kbyte program can be programmed into a DS2250(T) with little or no modification. This initialization automatically sets the range address for 8 kbytes and maps the lowest 4-kbyte bank of embedded RAM as program memory. The next 4 kbytes of embedded RAM are mapped as data memory. In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32 kbyte Program/Verify cycles take much longer than the normal 4 kbyte Program/Verify cycles.
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DS2250(T)
A typical parallel loading session would follow this procedure. First, set the contents of the MCON register with the correct range and partition only if using expanded programming cycles. Next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). Then, program the DS2250(T) using either normal or expanded program cycles and check the memory contents using Verify cycles. The last operation would be to turn on the security lock feature by either a Security Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.
SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 2
CRYSTAL FREQ (MHz) 14.7456 11.0592 9.21600 7.37280 5.52960 1.84320 BAUD RATE 300 Y Y Y Y Y 1200 Y Y Y Y Y Y 2400 Y Y Y Y Y Y 9600 Y Y Y Y Y Y 19200 Y Y 57600 Y
ADDITIONAL INFORMATION
A complete description for all operational aspects of the DS2250(T) is provided in the User's Guide section of the Secure Microcontroller Data Book.
DEVELOPMENT SUPPORT
Dallas Semiconductor offers a kit package for developing and testing user code. The DS5000TK Evaluation Kit allows the user to download Intel hex formatted code directly to the DS2250(T) from a PC-XT/AT or compatible computer. The kit consists of a DS5000T-32-12, an interface pod, demo software, and an RS232 connector that attaches to the COM1 or COM2 serial port of a PC. The kit can be used with a DS2250(T). A mechanical adapter, the DS9075-40V, allows a DS2250(T) to be used in the DS5000TK. See the Secure microcontroller User's Guide for further details.
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DS2250(T)
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V 0C to 70C -40C to +70C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC CHARACTERISTICS
PARAMETER Input Low Voltage Input High Voltage Input High Voltage RST, XTAL1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3) Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE, PSEN ) Output High Voltage @ IOH=-80 A (Ports 1, 2, 3) Output High Voltage @ IOH=-400 A (Ports 0, ALE, PSEN ) Input Low Current VIN = 0.45V (Ports 1, 2, 3) Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) Input Leakage Current 0.45 < VIN < VCC (Port 0) RST, EA Pulldown Resistor Stop Mode Current Power Fail Warning Voltage Minimum Operating Voltage Programming Supply Voltage (Parallel Program Mode) Program Supply Current Operating Current DS2250-8k DS2250-32k @ 12 MHz DS2250(T)-64-16 @ 16 MHz Idle Mode Current @ 8 MHz SYMBOL VIL VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL IL RRE ISM VPFW VCCmin VPP IPP ICC 4.15 4.05 12.5 40 2.4 2.4 MIN -0.3 2.0 3.5
(tA=0C to70C; VCC=5V 5%)
TYP MAX +0.8 VCC+0.3 VCC+0.3 0.15 0.15 4.8 4.8 -50 -500 10 125 80 4.6 4.5 4.75 4.65 13 15 20 43 48 54 6.2 0.45 0.45 UNITS V V V V V V V A A A k A V V V mA mA 2 4 1 1 1 1 1 1 NOTES 1 1 1
ICC
mA
3
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DS2250(T)
AC CHARACTERISTICS: EXPANDED BUS MODE TIMING SPECIFICATIONS
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr. In ALE Low to PSEN Low
PSEN PSEN
(tA=0C to70C; VCC=5V 5%)
SYMBOL 1/tCLK tALPW tAVALL tAVAAV MIN 1.0 2tCLK -40 tCLK -40 tCLK -35 4tCLK -150 4tCLK -90 tCLK -25 3tCLK -35 3tCLK -150 3tCLK -90 0 tCLK -20 tCLK -8 5tCLK -150 5tCLK -90 0 6tCLK -100 6tCLK -100 5tCLK -165 5tCLK -105 0 2tCLK -70 8CLK -150 8tCLK -90 9tCLK -165 9tCLK -105 3tCLK -50 4tCLK -130 tCLK -60 7tCLK -150 7tCLK -90 tCLK -50 0 tCLK -40 tCLK +50 3tCLK +50 MAX 16 (-16) UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
@ 12 MHz @ 16 MHz
tALLVI tALLPSL tPSPW
Pulse Width Low to Valid Instr. In @ 12 MHz @ 16 MHz
tPSLVI tPSIV tPSIX tPSAV tAVVI tPSLAZ tRDPW tWRPW
Input Instr. Hold after PSEN Going High Input Instr. Float after PSEN Going High Address Hold after PSEN Going High Address Valid to Valid Instr. In @ 12 MHz @ 16 MHz
PSEN
RD
Low to Address Float
Pulse Width Pulse Width Low to Valid Data In @ 12 MHz @ 16 MHz
WR
RD
tRDLDV tRDHDV tRDHDZ
Data Hold after RD High Data Float after RD High ALE Low to Valid Data In Valid Addr. to Valid Data In ALE Low to RD or WR Low Address Valid to RD or WR Low Data Valid to WR Going Low Data Valid to WR High Data Valid after WR High
RD RD
@ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz
tALLVD tAVDV tALLRDL tAVRDL tDVWRL tDVWRH tWRHDV tRDLAZ tRDHALH
@ 12 MHz @ 16 MHz
Low to Address Float or WR High to ALE High
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DS2250(T)
EXPANDED PROGRAM MEMORY READ CYCLE
EXPANDED DATA MEMORY READ CYCLE
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DS2250(T)
EXPANDED DATA MEMORY WRITE CYCLE
EXTERNAL CLOCK TIMING
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DS2250(T)
AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE
# 28 29 30 31 PARAMETER External Clock High Time External Clock Low Time External Clock Rise Time External Clock Fall Time @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz @ 12 MHz @ 16 MHz SYMBOL tCLKHPW tCLKLPW tCLKR tCLKF
(tA=0C to70C; VCC=5V 5%)
MIN 20 15 20 15 20 15 20 15 MAX UNITS ns ns ns ns ns ns ns ns
AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0
# 35 36 37 38 39 PARAMETER Serial Port Cycle Time Output Data Setup to Rising Clock Edge Output Data Hold after Rising Clock Edge Clock Rising Edge to Input Data Valid Input Data Hold after Rising Clock Edge SYMBOL tSPCLK tDOCH tCHDO tCHDV tCHDIV
(tA=0C to70C; VCC=5V 5%)
MIN 12tCLK 10tCLK -133 2tCLK -117 10tCLK -133 0 MAX UNITS s ns ns ns ns
SERIAL PORT TIMING - MODE 0
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DS2250(T)
AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING
# 32 33 34 PARAMETER Slew Rate from VCCmin to 3.3V Crystal Start-up Time Power-On Reset Delay SYMBOL tF tCSU tPOR
(tA=0C to70C; VCC=5V 5%)
MIN 40 MAX (note 5) 21504 tCLK UNITS s
POWER CYCLE TIMING
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DS2250(T)
AC CHARACTERISTICS (cont'd) PARALLEL PROGRAM LOAD TIMING
# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 PARAMETER Oscillator Frequency Address Setup to PROG Low Address Hold after PROG High Data Setup to PROG Low Data Hold after PROG High P2.7, 2.6, 2.5 Setup to VPP VPP Setup to PROG Low VPP Hold after PROG Low
PROG
(tA=0C to70C; VCC=5V 5%)
SYMBOL 1/tCLK tAVPRL tPRHAV tDVPRL tPRHDV tP27HVP tVPHPRL tPRHVPL tPRW tAVDV tDVP27L tP27HDZ tPORPV tRAVPH tVPPPC tVFT 0 21504 1200 1200 48 2400* MIN 1.0 0 0 0 0 0 0 0 2400 48 1800* 48 1800* 48 1800* tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK MAX 12.0 UNITS MHz
Width Low
Data Output from Address Valid Data Output from P2.7 Low Data Float after P2.7 High Delay to Reset/ PSEN Active after Power On Reset/ PSEN Active (or Verify Inactive) to VPP High VPP Inactive (Between Program Cycles) Verify Active Time
* Second set of numbers refers to expanded memory programming up to 32k bytes.
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DS2250(T)
PARALLEL PROGRAM LOAD TIMING
CAPACITANCE
PARAMETER Output Capacitance Input Capacitance SYMBOL CO CI MIN
(test frequency=1MHz; tA=25C)
TYP MAX 10 10 UNITS pF pF NOTES
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DS2250(T)
DS2250(T) TYPICAL ICC VS. FREQUENCY
FREQUENCY OF OPERATION (MHz) (VCC=+5V, tA=25C)
Normal operation is measured using: 1) External crystals on XTAL1 and 2 2) All port pins disconnected 3) RST=0 volts and EA=VCC 4) Part performing endless loop writing to internal memory Idle mode operation is measured using: 1) External clock source at XTAL1; XTAL2 floating 2) All port pins disconnected 3) RST=0 volts and EA=VCC 4) Part set in IDLE mode by software
NOTES:
1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC. 3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven at 8 MHz with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC, RST = VSS. 4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = VCC; XTAL2 not connected; RST = VSS. 5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for the worst case spec on this time. 18 of 20
DS2250(T)
PACKAGE DRAWING
PKG DIM A B C D E F G H I J K L M N O P
INCHES MIN 2.645 2.379 0.845 0.395 0.245 MAX 2.655 2.389 0.855 0.405 0.255
0.050 BSC 0.075 0.245 0.085 0.255
0.950 BSC 0.120 1.320 1.445 0.057 0.047 0.130 1.330 1.455 0.067 0.160 0.195 0.054
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DS2250(T)
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/13/95 and 08/16/96 version of the DS2250(T) data sheet. Please review this summary carefully. 1. Correct Figure 3 to show RST active high. 2. Add minimum value to PCB thickness.
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